Delay Lines
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Variable Delay Chip onsemi MC100EP195FAG with 10.2 Nanosecond Range and 2.2 Nanosecond Minimum Delay
Product Overview The MC10/100EP195 is a Programmable Delay Chip (PDC) designed for clock deskewing and timing adjustment. It offers variable delay for differential NECL/PECL input transitions with a digitally selectable resolution of approximately 10 ps and a net range of up to 10.2 ns. The delay is controlled by 10 data select inputs (D[9:0]) and the LEN pin for load and hold functions. The device features a fixed minimum delay of 2.2 ns and supports cascading for extended
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Precision Timing Control Dual Channel Programmable Delay onsemi NB6L295MNG with Cascaded Extended Delay Mode
NB6L295 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs Product Overview The NB6L295 is a versatile Dual Channel Programmable Delay Chip designed for precise clock or data de-skewing and timing adjustment. It offers two independent, configurable delay channels (PD0 and PD1) that can operate in either Dual Delay Mode or Extended Delay Mode. In Dual Delay Mode, each channel provides independent programmable delay. In Extended Delay Mode,
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Programmable delay chip onsemi NB6L295MMNG supporting LVPECL LVDS CML LVCMOS and LVTTL logic levels
Product Overview The NB6L295M is a dual-channel programmable clock/data delay chip designed for clock or data de-skewing and timing adjustment. It offers two individual variable delay channels (PD0 and PD1) that can operate in either Dual Delay Mode or Extended Delay Mode. In Dual Delay Mode, each channel provides independent programmable delay. In Extended Delay Mode, the delay of PD0 is cascaded with PD1 for additive delay. Programming is achieved via a 3-pin Serial Data
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3.3 Volt ECL Programmable Delay Device onsemi MC100EP195BMNG with 10 Nanosecond Variable Delay Range
Product Overview The MC100EP195B is a 3.3 V ECL Programmable Delay Chip (PDC) designed for clock deskewing and timing adjustment. It offers variable delay for differential NECL/PECL input transitions with a digitally selectable resolution of approximately 10 ps and a net range of up to 10.2 ns. The delay is controlled by 10 data select inputs (D[9:0]) and the LEN pin for transparent load or lock/hold modes. The device accepts LVPECL, LVDS, LVCMOS, or LVTTL level signals and
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Dual channel programmable delay chip Acelamicro ADLY89297 with 5Gbps speed and 1.3 to 6.1ns delay range
Product Overview The ADLY89297 is a dual-channel programmable delay chip designed for high-speed applications up to 5Gbps. It offers a delay range of 1.3ns to 6.1ns per channel with a minimum step of approximately 5ps and an INL error of around 15ps. The chip features a three-wire SPI serial data interface (SDATA, SCLK, SLOAD) for setting delay values, with each channel having a 10-bit control width. Multiple ADLY89297 chips can be cascaded for increased delay. Packaged in a
