Product Overview
The ADLY89297 is a dual-channel programmable delay chip designed for high-speed applications up to 5Gbps. It offers a delay range of 1.3ns to 6.1ns per channel with a minimum step of approximately 5ps and an INL error of around 15ps. The chip features a three-wire SPI serial data interface (SDATA, SCLK, SLOAD) for setting delay values, with each channel having a 10-bit control width. Multiple ADLY89297 chips can be cascaded for increased delay. Packaged in a compact 4x4mm QFN24, it operates reliably within an industrial temperature range of -40 to +85. Key applications include multi-channel clock synchronization and automatic test equipment.
Product Attributes
- Brand: ACELA
- Model: ADLY89297
- Packaging: QFN24 (4x4mm)
- Operating Temperature: Industrial (-40 to +85)
Technical Specifications
| Parameter | Min | Typical | Max | Unit | Notes |
|---|---|---|---|---|---|
| Dual-channel programmable delay line | |||||
| Serial Data Interface | SDATA, SCLK, SLOAD | ||||
| Operating Rate | DC | 5Gbps | |||
| Delay Range per Channel | 1.3 | 6.1 | ns | ||
| Minimum Step Size | 5 | ps | |||
| INL Error | 15 | ps | |||
| Channel Delay Control Bit Width | 10 | bits | |||
| Maximum Input Clock Frequency | 2.5GHz | ||||
| Differential Output Swing | 750 | mVpp | |||
| Power Supply Voltage (VCC) | 3.0 | 3.3 | 3.6 | V | |
| Power Supply Current (ICC) | 200 | 250 | mA | ||
| Differential Input Resistance | 90 | 100 | 110 | ||
| Common-mode Reference Voltage Output (VREF) | 2 | V | VCC=3.3V | ||
| Differential Output Voltage Swing | 750 | mV | |||
| Integral Non-Linearity (INL) | -15 | +15 | ps | ||
| Setup Time (SDATA to SCLK) | 400 | ps | Design Guaranteed | ||
| Hold Time (SLOAD to SCLK) | 300 | ps | Design Guaranteed |
Application Scenarios
- Multi-channel clock synchronization
- Automatic test equipment
2512101755_Acelamicro-ADLY89297_C53145109.pdf
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