Si510/511 CRYSTAL OSCILLATOR (XO)
The Si510/511 XO utilizes Skyworks Solutions' advanced DSPLL technology to provide any frequency from 100 kHz to 250 MHz. Unlike traditional XOs requiring a different crystal for each output frequency, the Si510/511 uses one fixed crystal and Skyworks Solutions proprietary DSPLL synthesizer. This IC-based approach offers enhanced reliability, improved mechanical robustness, and excellent stability. It also provides superior supply noise rejection, simplifying low jitter clock generation in noisy environments. Crystal ESR and DLD are individually production-tested to guarantee performance and enhance reliability. The Si510/511 is factory-configurable for a wide variety of user specifications, including frequency, supply voltage, output format, output enable polarity, and stability, eliminating long lead times and NRE charges associated with custom frequency oscillators.
Product Attributes
- Brand: Skyworks Solutions, Inc.
- Technology: DSPLL
- Certifications: Pb-free, RoHS compliant
Applications
- SONET/SDH/OTN
- Gigabit Ethernet
- Fibre Channel/SAS/SATA
- PCI Express
- 3G-SDI/HD-SDI/SDI
- Telecom
- Switches/routers
- FPGA/ASIC clock generation
Technical Specifications
| Parameter | Symbol | Test Condition | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| Operating Specifications (VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 °C) | ||||||
| Supply Voltage (3.3 V option) | VDD | 2.97 | 3.3 | 3.63 | V | |
| Supply Voltage (2.5 V option) | VDD | 2.25 | 2.5 | 2.75 | V | |
| Supply Voltage (1.8 V option) | VDD | 1.71 | 1.8 | 1.89 | V | |
| Supply Current (CMOS, 100 MHz, single-ended) | IDD | 21 | 26 | mA | ||
| Supply Current (LVDS, output enabled) | IDD | 19 | 23 | mA | ||
| Supply Current (LVPECL, output enabled) | IDD | 39 | 43 | mA | ||
| Supply Current (HCSL, output enabled) | IDD | 41 | 44 | mA | ||
| Supply Current (Tristate, output disabled) | IDD | 18 | mA | |||
| OE "1" Setting VIH | See Note | 0.80 x VDD | V | |||
| OE "0" Setting VIL | See Note | 0.20 x VDD | V | |||
| OE Internal Pull-Up/Pull-Down Resistor | RI | 45 | kΩ | |||
| Operating Temperature | TA | –40 | 85 | °C | ||
| Output Clock Frequency Characteristics (VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 °C) | ||||||
| Nominal Frequency (CMOS, Dual CMOS) | FO | 0.1 | 212.5 | MHz | ||
| Nominal Frequency (LVDS/LVPECL/HCSL) | FO | 0.1 | 250 | MHz | ||
| Total Stability (Grade C) | –30 | +30 | ppm | |||
| Total Stability (Grade B) | –50 | +50 | ppm | |||
| Total Stability (Grade A) | –100 | +100 | ppm | |||
| Temperature Stability (Grade C) | –20 | +20 | ppm | |||
| Temperature Stability (Grade B) | –25 | +25 | ppm | |||
| Temperature Stability (Grade A) | –50 | +50 | ppm | |||
| Startup Time | TSU | Minimum VDD until output frequency (FO) within specification | 10 | ms | ||
| Disable Time (FO ≥10 MHz) | TD | 5 | µs | |||
| Disable Time (FO <10 MHz) | TD | 40 | µs | |||
| Enable Time (FO ≥10 MHz) | TE | 20 | µs | |||
| Enable Time (FO <10 MHz) | TE | 60 | µs | |||
| Output Clock Levels and Symmetry (VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 °C) | ||||||
| CMOS Output Logic High | VOH | 0.85 x VDD | V | |||
| CMOS Output Logic Low | VOL | 0.15 x VDD | V | |||
| CMOS Output Rise/Fall Time (20 to 80% VDD, 0.1 to 212.5 MHz, CL = 15 pF) | TR/TF | 0.45 | 0.8 | 1.2 | ns | |
| CMOS Output Rise/Fall Time (20 to 80% VDD, 0.1 to 212.5 MHz, CL = no load) | TR/TF | 0.3 | 0.6 | 0.9 | ns | |
| LVPECL Output Rise/Fall Time (20 to 80% VDD) | TR/TF | 100 | 565 | ps | ||
| HCSL Output Rise/Fall Time (20 to 80% VDD) | TR/TF | 100 | 470 | ps | ||
| LVDS Output Rise/Fall Time (20 to 80% VDD) | TR/TF | 350 | 800 | ps | ||
| LVPECL Output Common Mode (50 Ω to VDD – 2 V, single-ended) | VOC | VDD – 1.4 V | V | |||
| LVPECL Output Swing (50 Ω to VDD – 2 V, single-ended) | VO | 0.55 | 0.8 | 0.90 | VPPSE | |
| LVDS Output Common Mode (100 Ω line-line, VDD = 3.3/2.5 V) | VOC | 1.13 | 1.23 | 1.33 | V | |
| LVDS Output Common Mode (100 Ω line-line, VDD = 1.8 V) | VOC | 0.83 | 0.92 | 1.00 | V | |
| LVDS Output Swing (Single-ended, 100 Ω differential termination) | VO | 0.25 | 0.35 | 0.45 | VPPSE | |
| HCSL Output Common Mode (50 Ω to ground) | VOC | 0.35 | 0.38 | 0.42 | V | |
| HCSL Output Swing (Single-ended) | VO | 0.58 | 0.73 | 0.85 | VPPSE | |
| Duty Cycle (All formats) | DC | 48 | 50 | 52 | % | |
| Output Clock Jitter and Phase Noise (LVPECL) (VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 °C; Output Format = LVPECL) | ||||||
| Period Jitter (RMS, 10k samples) | JPRMS | 1.3 | ps | |||
| Period Jitter (Pk-Pk, 10k samples) | JPPKPK | 11 | ps | |||
| Phase Jitter (RMS, 1.875 MHz to 20 MHz integration bandwidth) | φJ | (brickwall) | 0.31 | 0.5 | ps | |
| Phase Jitter (RMS, 12 kHz to 20 MHz integration bandwidth) | φJ | (brickwall) | 0.8 | 1.0 | ps | |
| Phase Noise (156.25 MHz, 100 Hz offset) | φN | –86 | dBc/Hz | |||
| Phase Noise (156.25 MHz, 1 kHz offset) | φN | –109 | dBc/Hz | |||
| Phase Noise (156.25 MHz, 10 kHz offset) | φN | –116 | dBc/Hz | |||
| Phase Noise (156.25 MHz, 100 kHz offset) | φN | –123 | dBc/Hz | |||
| Phase Noise (156.25 MHz, 1 MHz offset) | φN | –136 | dBc/Hz | |||
| Additive RMS Jitter Due to External Power Supply Noise (10 kHz sinusoidal noise) | JPSR | 3.0 | ps | |||
2411041604_SKYWORKS-510FCB-CAAG_C7187204.pdf
Please Use Our Online Inquiry Contact Form Below If You Have Any Questions, Our Team Will Get Back To You As Soon As Possible
