Skyworks Solutions Si510/511 Crystal Oscillator (XO)
The Si510/511 XO utilizes Skyworks Solutions' advanced DSPLL technology to provide any frequency from 100 kHz to 250 MHz using a single fixed crystal and a proprietary DSPLL synthesizer. This IC-based approach enhances reliability, mechanical robustness, and stability, while offering superior supply noise rejection for low jitter clock generation in noisy environments. Crystal ESR and DLD are individually production-tested for guaranteed performance and reliability. The Si510/511 is factory-configurable for various user specifications, including frequency, supply voltage, output format, output enable polarity, and stability, eliminating long lead times and NRE charges associated with custom frequency oscillators.
Product Attributes
- Brand: Skyworks Solutions
- Technology: DSPLL
- Certifications: Pb-free, RoHS compliant
- Package Options: 5 x 7 mm, 3.2 x 5 mm, 2.5 x 3.2 mm
- Operating Temperature: 40 to 85 C
Applications
- SONET/SDH/OTN
- Gigabit Ethernet
- Fibre Channel/SAS/SATA
- PCI Express
- 3G-SDI/HD-SDI/SDI
- Telecom
- Switches/routers
- FPGA/ASIC clock generation
Technical Specifications
| Parameter | Symbol | Test Condition | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| Operating Specifications (VDD = 1.8 V 5%, 2.5 or 3.3 V 10%, TA = 40 to +85 C) | ||||||
| Supply Voltage (3.3 V option) | VDD | 2.97 | 3.3 | 3.63 | V | |
| Supply Voltage (2.5 V option) | VDD | 2.25 | 2.5 | 2.75 | V | |
| Supply Voltage (1.8 V option) | VDD | 1.71 | 1.8 | 1.89 | V | |
| Supply Current (CMOS, 100 MHz, single-ended) | IDD | 21 | 26 | mA | ||
| Supply Current (LVDS, output enabled) | IDD | 19 | 23 | mA | ||
| Supply Current (LVPECL, output enabled) | IDD | 39 | 43 | mA | ||
| Supply Current (HCSL, output enabled) | IDD | 41 | 44 | mA | ||
| Supply Current (Tristate, output disabled) | IDD | 18 | mA | |||
| Output Clock Frequency Characteristics (VDD = 1.8 V 5%, 2.5 or 3.3 V 10%, TA = 40 to +85 C) | ||||||
| Nominal Frequency (CMOS, Dual CMOS) | FO | 0.1 | 212.5 | MHz | ||
| Nominal Frequency (LVDS/LVPECL/HCSL) | FO | 0.1 | 250 | MHz | ||
| Total Stability (Grade C) | 30 | +30 | ppm | |||
| Total Stability (Grade B) | 50 | +50 | ppm | |||
| Total Stability (Grade A) | 100 | +100 | ppm | |||
| Startup Time | TSU | Minimum VDD until output frequency (FO) within specification | 10 | ms | ||
| Disable Time (FO 10 MHz) | TD | 5 | s | |||
| Disable Time (FO < 10 MHz) | TD | 40 | s | |||
| Enable Time (FO 10 MHz) | TE | 20 | s | |||
| Enable Time (FO < 10 MHz) | TE | 60 | s | |||
| Output Clock Levels and Symmetry (VDD = 1.8 V 5%, 2.5 or 3.3 V 10%, TA = 40 to +85 C) | ||||||
| CMOS Output Rise/Fall Time (20 to 80% VDD, CL = 15 pF) | TR/TF | 0.1 to 212.5 MHz | 0.45 | 0.8 | 1.2 | ns |
| CMOS Output Rise/Fall Time (20 to 80% VDD, CL = no load) | TR/TF | 0.1 to 212.5 MHz | 0.3 | 0.6 | 0.9 | ns |
| LVPECL Output Rise/Fall Time (20 to 80% VDD) | TR/TF | 100 | 565 | ps | ||
| HCSL Output Rise/Fall Time (20 to 80% VDD) | TR/TF | 100 | 470 | ps | ||
| LVDS Output Rise/Fall Time (20 to 80% VDD) | TR/TF | 350 | 800 | ps | ||
| Duty Cycle | DC | All formats | 48 | 50 | 52 | % |
| Output Clock Jitter and Phase Noise (LVPECL) (VDD = 2.5 or 3.3 V 10%, TA = 40 to +85 C; Output Format = LVPECL) | ||||||
| Period Jitter (RMS) | JPRMS | 10k samples | 1.3 | ps | ||
| Period Jitter (Pk-Pk) | JPPKPK | 10k samples | 11 | ps | ||
| Phase Jitter (RMS) (1.875 MHz to 20 MHz integration bandwidth) | J | (brickwall) | 0.31 | 0.5 | ps | |
| Phase Jitter (RMS) (12 kHz to 20 MHz integration bandwidth) | J | (brickwall) | 0.8 | 1.0 | ps | |
| Phase Noise (156.25 MHz, 100 Hz offset) | N | 86 | dBc/Hz | |||
| Phase Noise (156.25 MHz, 1 kHz offset) | N | 109 | dBc/Hz | |||
| Phase Noise (156.25 MHz, 10 kHz offset) | N | 116 | dBc/Hz | |||
| Phase Noise (156.25 MHz, 100 kHz offset) | N | 123 | dBc/Hz | |||
| Phase Noise (156.25 MHz, 1 MHz offset) | N | 136 | dBc/Hz | |||
| Additive RMS Jitter Due to External Power Supply Noise (10 kHz sinusoidal noise) | JPSR | 3.0 | ps | |||
2411041604_SKYWORKS-511QCB-ABAG_C7024363.pdf
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