Product Overview
The Skyworks Solutions Si545 Ultra Series Crystal Oscillator is an ultra-low jitter, low phase noise clock generator utilizing advanced 4th generation DSPLL technology. It offers any-frequency output from 0.2 to 1500 MHz with <1 ppb resolution, maintaining exceptionally low jitter across its operating range. The Si545 provides excellent reliability, frequency stability, and guaranteed aging performance. Its on-chip power supply filtering offers industry-leading power supply noise rejection, simplifying low-jitter clock generation in noisy systems. The device is factory-programmed to user specifications, enabling rapid sample delivery (1-2 weeks). This oscillator is ideal for applications such as 100G/200G/400G OTN, 10G/40G/100G optical Ethernet, broadcast video, datacenters, test and measurement, clock and data recovery, and FPGA/ASIC clocking.
Product Attributes
- Brand: Skyworks Solutions
- Technology: 4th generation DSPLL
- Output Frequency Range: 0.2 to 1500 MHz
- Frequency Resolution: <1 ppb
- Lead Time for Custom Frequency Samples: 1-2 weeks
Technical Specifications
| Parameter | Symbol | Test Condition/Comment | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| Temperature Range | TA | -40 | 85 | C | ||
| Frequency Range (LVPECL, LVDS, CML) | FCLK | 0.2 | 1500 | MHz | ||
| Frequency Range (HCSL) | FCLK | 0.2 | 400 | MHz | ||
| Frequency Range (CMOS, Dual CMOS) | FCLK | 0.2 | 250 | MHz | ||
| Supply Voltage (3.3 V option) | VDD | 3.135 | 3.3 | 3.465 | V | |
| Supply Voltage (2.5 V option) | VDD | 2.375 | 2.5 | 2.625 | V | |
| Supply Voltage (1.8 V option) | VDD | 1.71 | 1.8 | 1.89 | V | |
| Supply Current (LVPECL, output enabled) | IDD | 107 | 153 | mA | ||
| Supply Current (LVDS/CML, output enabled) | IDD | 83 | 121 | mA | ||
| Supply Current (HCSL, output enabled) | IDD | 86 | 126 | mA | ||
| Supply Current (HCSL-Fast, output enabled) | IDD | 94 | 138 | mA | ||
| Supply Current (CMOS, output enabled) | IDD | 87 | 127 | mA | ||
| Supply Current (Dual CMOS, output enabled) | IDD | 92 | 141 | mA | ||
| Supply Current (Tristate, output disabled) | IDD | 73 | 112 | mA | ||
| Frequency Stability (Grade A) | Temperature stability | -20 | 20 | ppm | ||
| Frequency Stability (Grade B) | Temperature stability | -10 | 10 | ppm | ||
| Frequency Stability (Grade C) | Temperature stability | -7 | 7 | ppm | ||
| Total Stability (Grade A) | FSTAB | -50 | 50 | ppm | ||
| Total Stability (Grade B) | FSTAB | -25 | 25 | ppm | ||
| Total Stability (Grade C) | FSTAB | -20 | 20 | ppm | ||
| Rise/Fall Time (LVPECL/LVDS/CML) | TR/TF | (20% to 80% VPP) | 350 | ps | ||
| Rise/Fall Time (CMOS / Dual CMOS, CL = 5 pF) | TR/TF | (20% to 80% VPP) | 0.5 | 1.5 | ns | |
| Rise/Fall Time (HCSL, FCLK >50 MHz) | TR/TF | (20% to 80% VPP) | 550 | ps | ||
| Rise/Fall Time (HCSL-Fast, FCLK >50 MHz) | TR/TF | (20% to 80% VPP) | 275 | ps | ||
| Duty Cycle | DC | All formats | 45 | 55 | % | |
| Output Enable VIH | OE | 0.7 VDD | V | |||
| Output Enable VIL | OE | 0.3 VDD | V | |||
| Output Disable Time (FCLK > 10 MHz) | TD | 3 | s | |||
| Output Enable Time (FCLK > 10 MHz) | TE | 20 | s | |||
| Powerup Time | tOSC | Time from 0.9 VDD until output frequency (FCLK) within spec | 10 | ms | ||
| Powerup VDD Ramp Rate | VRAMP | Fastest VDD ramp rate allowed on startup | 100 | V/ms | ||
| Phase Jitter (RMS, 12kHz - 20MHz) (3.2 x 5 mm, FCLK 200 MHz) | J | All Differential Formats | 80 | 110 | fs | |
| Phase Jitter (RMS, 12kHz - 20MHz) (3.2 x 5 mm, 100 MHz FCLK < 200 MHz) | J | All Differential Formats | 100 | 150 | fs | |
| Phase Jitter (RMS, 12kHz - 20MHz) (5 x 7 mm, FCLK 200 MHz) | J | All Differential Formats | 80 | 130 | fs | |
| Phase Jitter (RMS, 12kHz - 20MHz) (5 x 7 mm, 100 MHz FCLK < 200 MHz) | J | All Differential Formats | 100 | 150 | fs | |
| Phase Jitter (RMS, 12kHz - 20MHz) (2.5 x 3.2 mm, FCLK 200 MHz) | J | All Differential Formats | 90 | 130 | fs | |
| Phase Jitter (RMS, 12kHz - 20MHz) (2.5 x 3.2 mm, 100 MHz FCLK < 200 MHz) | J | All Differential Formats | 100 | 150 | fs | |
| Phase Jitter (RMS, 12kHz - 20MHz) (CMOS / Dual CMOS Formats) | J | 10 MHz FCLK 250 MHz | 200 | fs | ||
| Spurs Induced by External Power Supply Noise (LVDS, 156.25 MHz Output) | PSNR | 50 mVpp Ripple, 100 kHz sine wave | -83 | dBc | ||
| Spurs Induced by External Power Supply Noise (LVDS, 156.25 MHz Output) | PSNR | 50 mVpp Ripple, 200 kHz sine wave | -83 | dBc | ||
| Spurs Induced by External Power Supply Noise (LVDS, 156.25 MHz Output) | PSNR | 50 mVpp Ripple, 500 kHz sine wave | -82 | dBc | ||
| Spurs Induced by External Power Supply Noise (LVDS, 156.25 MHz Output) | PSNR | 50 mVpp Ripple, 1 MHz sine wave | -85 | dBc | ||
| Package Options | 2.53.2 mm, 3.25 mm, 57 mm | |||||
| Output Format Options | LVPECL, LVDS, CML, HCSL, CMOS, Dual CMOS | |||||
| Total Stability (includes temp, initial accuracy, load pulling, VDD variation, and 20 yr aging at 70 C) | FSTAB | 20 | ppm | |||
2411061616_SKYWORKS-545CCA25M0000CCG_C22264026.pdf
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