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Specifications
Mfr. Part #:
511BBA125M000BAGR
Package:
SMD5032-6P
Key Attributes
Model Number:
511BBA125M000BAGR
Product Description
Product Overview
The Si510/511 Crystal Oscillator (XO) from Silicon Laboratories utilizes advanced DSPLL technology to provide any frequency from 100 kHz to 250 MHz. This IC-based solution uses a single fixed crystal and a proprietary synthesizer, offering enhanced reliability, improved mechanical robustness, and excellent stability compared to traditional XOs. It features superior supply noise rejection, simplifying low jitter clock generation in noisy environments. The Si510/511 is factory-configurable for various user specifications, including frequency, supply voltage, output format, and stability, with short lead times and no NRE charges for custom configurations.
Product Attributes
- Brand: Silicon Laboratories
- Technology: DSPLL
- Certifications: Pb-free, RoHS compliant
- Package Options: 5 x 7 mm, 3.2 x 5 mm, 2.5 x 3.2 mm
- Operating Temperature: 40 to 85 C
Technical Specifications
| Parameter | Symbol | VDD | TA (C) | Min | Typ | Max | Unit | Notes |
| Supply Voltage | VDD | 3.3 V 10% | 40 to 85 | 2.97 | 3.3 | 3.63 | V | |
| VDD | 2.5 V 10% | 40 to 85 | 2.25 | 2.5 | 2.75 | V | ||
| VDD | 1.8 V 5% | 40 to 85 | 1.71 | 1.8 | 1.89 | V | ||
| Supply Current (CMOS, 100 MHz, single-ended) | IDD | All | 40 to 85 | 21 | 26 | mA | ||
| Supply Current (LVDS, output enabled) | IDD | All | 40 to 85 | 19 | 23 | mA | ||
| Supply Current (LVPECL, output enabled) | IDD | All | 40 to 85 | 39 | 43 | mA | ||
| Supply Current (HCSL, output enabled) | IDD | All | 40 to 85 | 41 | 44 | mA | ||
| Supply Current (Tristate, output disabled) | IDD | All | 40 to 85 | 18 | mA | |||
| OE "1" Setting | VIH | All | 40 to 85 | 0.80 x VDD | V | See Note | ||
| OE "0" Setting | VIL | All | 40 to 85 | 0.20 x VDD | V | See Note | ||
| OE Internal Pull-Up/Pull-Down Resistor | RI | All | 40 to 85 | 45 | k | *Note: Active high and active low polarity OE options available. Active high option includes an internal pull-up. Active low option includes an internal pull-down. | ||
| Nominal Frequency (CMOS, Dual CMOS) | FO | All | 40 to 85 | 0.1 | 212.5 | MHz | ||
| FO | All | 40 to 85 | 0.1 | 250 | MHz | LVDS/LVPECL/HCSL | ||
| Total Stability (includes 10-year aging) | Frequency Stability Grade C | All | 40 to 85 | 30 | +30 | ppm | ||
| Frequency Stability Grade B | All | 40 to 85 | 50 | +50 | ppm | |||
| Frequency Stability Grade A | All | 40 to 85 | 100 | +100 | ppm | |||
| Startup Time | TSU | All | 40 to 85 | 10 | ms | Minimum VDD until output frequency (FO) within specification | ||
| Disable Time (FO 10 MHz) | TD | All | 40 to 85 | 5 | s | |||
| Disable Time (FO < 10 MHz) | TD | All | 40 to 85 | 40 | s | |||
| Enable Time (FO 10 MHz) | TE | All | 40 to 85 | 20 | s | |||
| Enable Time (FO < 10 MHz) | TE | All | 40 to 85 | 60 | s | |||
| CMOS Output Logic High | VOH | All | 40 to 85 | 0.85 x VDD | V | |||
| CMOS Output Logic Low | VOL | All | 40 to 85 | 0.15 x VDD | V | |||
| CMOS Output Rise/Fall Time (20 to 80% VDD, CL = 15 pF) | TR/TF | All | 40 to 85 | 0.45 | 0.8 | 1.2 | ns | 0.1 to 212.5 MHz |
| LVPECL Output Rise/Fall Time (20 to 80% VDD) | TR/TF | All | 40 to 85 | 100 | 565 | ps | ||
| HCSL Output Rise/Fall Time (20 to 80% VDD) | TR/TF | All | 40 to 85 | 100 | 470 | ps | ||
| LVDS Output Rise/Fall Time (20 to 80% VDD) | TR/TF | All | 40 to 85 | 350 | 800 | ps | ||
| LVPECL Output Common Mode | VOC | All | 40 to 85 | VDD 1.4 | V | 50 to VDD 2 V, single-ended | ||
| LVDS Output Common Mode (VDD = 3.3/2.5 V) | VOC | 3.3/2.5 V | 40 to 85 | 1.13 | 1.23 | 1.33 | V | 100 line-line |
| LVDS Output Common Mode (VDD = 1.8 V) | VOC | 1.8 V | 40 to 85 | 0.83 | 0.92 | 1.00 | V | 100 line-line |
| HCSL Output Common Mode | VOC | All | 40 to 85 | 0.35 | 0.38 | 0.42 | V | 50 to ground |
| Duty Cycle | DC | All | 40 to 85 | 48 | 50 | 52 | % | All formats |
| Period Jitter (RMS, 10k samples) | JPRMS | All | 40 to 85 | 1.3 | ps | LVPECL | ||
| Period Jitter (RMS, 10k samples) | JPRMS | All | 40 to 85 | 2.1 | ps | LVDS | ||
| Phase Jitter (RMS, 1.875 MHz to 20 MHz) | J | All | 40 to 85 | 0.31 | 0.5 | ps | LVPECL | |
| Phase Jitter (RMS, 1.875 MHz to 20 MHz) | J | All | 40 to 85 | 0.25 | 0.55 | ps | LVDS | |
| Phase Noise (100 Hz offset, 156.25 MHz) | N | All | 40 to 85 | 86 | dBc/Hz | LVPECL/LVDS | ||
| Phase Noise (1 kHz offset, 156.25 MHz) | N | All | 40 to 85 | 109 | dBc/Hz | LVPECL/LVDS | ||
| Phase Noise (10 kHz offset, 156.25 MHz) | N | All | 40 to 85 | 116 | dBc/Hz | LVPECL/LVDS | ||
| Phase Noise (100 kHz offset, 156.25 MHz) | N | All | 40 to 85 | 123 | dBc/Hz | LVPECL/LVDS | ||
| Phase Noise (1 MHz offset, 156.25 MHz) | N | All | 40 to 85 | 136 | dBc/Hz | LVPECL/LVDS | ||
| Additive RMS Jitter (10 kHz sinusoidal noise) | JPSR | All | 40 to 85 | 3.0 | ps | LVPECL/LVDS, 156.25 MHz | ||
| Spurious (offset > 10 kHz, 156.25 MHz) | SPR | All | 40 to 85 | 75 | dBc | LVPECL/LVDS |
Applications
- SONET/SDH/OTN
- Gigabit Ethernet
- Fibre Channel/SAS/SATA
- PCI Express
- 3G-SDI/HD-SDI/SDI
- Telecom
- Switches/routers
- FPGA/ASIC clock generation
2410121928_SILICON-LABS-511BBA125M000BAGR_C1987721.pdf
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