Skyworks Solutions Si535/536 ULTRA LOW JITTER CRYSTAL OSCILLATOR (XO)
The Si535/536 XO utilizes Skyworks Solutions advanced DSPLL circuitry to provide an ultra low jitter clock at high-speed differential frequencies. Unlike traditional XOs, it uses one fixed crystal to generate a wide range of output frequencies, ensuring exceptional frequency stability and reliability. Its IC-based design offers superior supply noise rejection, simplifying low-jitter clock generation in noisy communication system environments. Factory programmed at shipment, it eliminates long lead times associated with custom oscillators.
Product Attributes
- Brand: Skyworks Solutions, Inc.
- Technology: DSPLL circuitry
- Package: Industry-standard 5 x 7 mm
- Compliance: Pb-free/RoHS-compliant
- Certifications: MIL-STD-883 (Shock, Vibration, Solderability, Leak, Solder Heat), J-STD-020 (Moisture Sensitivity Level MSL1)
Technical Specifications
| Parameter | Symbol | Test Condition | Min | Typ | Max | Unit | Notes |
| Recommended Operating Conditions | |||||||
| Supply Voltage (3.3 V option) | VDD | 2.97 | 3.3 | 3.63 | V | Selectable parameter specified by part number. | |
| Supply Voltage (2.5 V option) | VDD | 2.25 | 2.5 | 2.75 | V | Selectable parameter specified by part number. | |
| Supply Current (Output enabled, LVPECL) | IDD | 111 | 121 | mA | |||
| Supply Current (Output enabled, LVDS) | IDD | 90 | 98 | mA | |||
| Supply Current (Tristate mode) | IDD | 60 | 75 | mA | |||
| Output Enable (OE) High Input Voltage | VIH | 0.75 x VDD | 0.75 | V | OE pin includes a 17 k pullup resistor to VDD. | ||
| Output Enable (OE) Low Input Voltage | VIL | 0.5 | V | OE pin includes a 17 k pullup resistor to VDD. | |||
| Operating Temperature Range | TA | 40 | 85 | C | |||
| CLK Output Frequency Characteristics | |||||||
| Nominal Frequency | fO | LVPECL/LVDS | 100 | 312.5 | MHz | See Section 3. "Ordering Information" for list of available frequencies. | |
| Initial Accuracy | fi | Measured at +25 C at time of shipping | 1.5 | ppm | |||
| Temperature Stability (20 ppm option) | 20 | +20 | ppm | Selectable parameter specified by part number. | |||
| Temperature Stability (7 ppm option) | 7 | +7 | ppm | Selectable parameter specified by part number. | |||
| Aging (Frequency drift over first year) | fa | 3 | ppm | ||||
| Aging (Frequency drift over 20 year life) | fa | 10 | ppm | ||||
| Total Stability (Temp stability = 20 ppm) | 31.5 | ppm | |||||
| Total Stability (Temp stability = 7 ppm) | 20 | ppm | |||||
| Powerup Time | tOSC | TA = 40C to +85C | 10 | ms | Time from powerup or tristate mode to fO. | ||
| CLK Output Levels and Symmetry | |||||||
| LVPECL Mid-level Voltage | VO | 50 to VDD 2.0 V | VDD 1.42 | VDD 1.25 | V | ||
| LVPECL Differential Swing | VOD | 1.1 | 1.9 | VPP | |||
| LVPECL Single-ended Swing | VSE | 0.55 | 0.95 | VPP | |||
| LVDS Mid-level Voltage | VO | Rterm = 100 (differential) | 1.125 | 1.20 | 1.275 | V | |
| LVDS Differential Swing | VOD | Rterm = 100 (differential) | 0.5 | 0.7 | 0.9 | VPP | |
| Rise/Fall time (20/80%) | tR, tF | 350 | ps | ||||
| Symmetry (duty cycle) | SYM | Differential | 45 | 55 | % | ||
| CLK Output Phase Jitter | |||||||
| Phase Jitter* (RMS) | J | 10 kHz to 1 MHz (data center) | 0.19 | 0.35 | ps | Applies to output frequencies: 156.25 MHz. | |
| Phase Jitter* (RMS) | J | 12 kHz to 20 MHz brickwall | 0.25 | 0.40 | ps | Applies to output frequencies: 156.25 MHz. | |
| CLK Output Period Jitter | |||||||
| Period Jitter* (RMS) | JPER | N = 1000 cycles | 2 | ps | |||
| Period Jitter* (Peak-to-Peak) | JPER | N = 1000 cycles | 14 | ps | |||
| Thermal Characteristics | |||||||
| Thermal Resistance Junction to Ambient | JA | Still Air, TA = 25 C, VDD = 3.3 V | 84.6 | C/W | |||
| Thermal Resistance Junction to Case | JC | Still Air, TA = 25 C, VDD = 3.3 V | 38.8 | C/W | |||
| Ambient Temperature | TA | 40 | 85 | C | |||
| Junction Temperature | TJ | 125 | C | ||||
| Absolute Maximum Ratings | |||||||
| Maximum Operating Temperature | TAMAX | 85 | C | Stresses beyond those listed may cause permanent damage. | |||
| Supply Voltage (2.5/3.3 V Option) | VDD | 0.5 | +3.8 | V | Stresses beyond those listed may cause permanent damage. | ||
| Input Voltage (any input pin) | VI | 0.5 | VDD + 0.3 | V | Stresses beyond those listed may cause permanent damage. | ||
| Storage Temperature | TS | 55 | +125 | C | Stresses beyond those listed may cause permanent damage. | ||
| ESD Sensitivity (HBM, per JESD22-A114) | ESD | 2500 | V | ||||
| Soldering Temperature (Pb-free profile) | TPEAK | 260 | C | Compliant with JEDEC J-STD-020C. | |||
| Soldering Temperature Time @ TPEAK (Pb-free profile) | tP | 20 | 40 | seconds | Compliant with JEDEC J-STD-020C. | ||
2508281722_SILICON-LABS-536EB212M500DGR_C2029920.pdf
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