Skyworks Si535/536 Ultra Low Jitter Crystal Oscillator (XO)
The Si535/536 XO utilizes Skyworks Solutions advanced DSPLL circuitry to provide an ultra low jitter clock at high-speed differential frequencies. Unlike traditional XOs that require a unique crystal for each output frequency, the Si535/536 uses a single fixed crystal to generate a wide range of output frequencies. This IC-based approach ensures exceptional frequency stability and reliability. The DSPLL clock synthesis offers superior supply noise rejection, simplifying the generation of low jitter clocks in noisy communication system environments. The Si535/536 IC-based XO is factory programmed at shipment, eliminating long lead times associated with custom oscillators. It is ideal for demanding applications such as 10/40/100G data centers, 10G Ethernet switches/routers, Fibre Channel/SAS/storage, enterprise servers, networking, and telecommunications.
Product Attributes
- Brand: Skyworks Solutions, Inc.
- Technology: DSPLL circuitry
- Package: Industry-standard 5 x 7 mm
- Compliance: Pb-free/RoHS-compliant
Technical Specifications
| Parameter | Symbol | Test Condition | Min | Typ | Max | Unit | Notes |
| Supply Voltage | VDD | 3.3 V option | 2.97 | 3.3 | 3.63 | V | Selectable parameter specified by part number. |
| VDD | 2.5 V option | 2.25 | 2.5 | 2.75 | V | Selectable parameter specified by part number. | |
| Supply Current | IDD | Output enabled LVPECL | 111 | 121 | mA | ||
| IDD | Output enabled LVDS | 90 | 98 | mA | |||
| Output Enable (OE) | VIH | 0.75 x VDD | V | OE pin includes a 17 k pullup resistor to VDD. | |||
| Output Enable (OE) | VIL | 0.5 | V | OE pin includes a 17 k pullup resistor to VDD. | |||
| Operating Temperature Range | TA | -40 | 85 | C | |||
| Frequency Stability | fi | Initial Accuracy Measured at +25 C at time of shipping | 1.5 | ppm | See Section 3. "Ordering Information" on page 7 for the list of available frequencies. | ||
| Temperature Stability | -7 to +7 ppm option | -7 | +7 | ppm | Selectable parameter specified by part number. | ||
| Temperature Stability | -20 to +20 ppm option | -20 | +20 | ppm | Selectable parameter specified by part number. | ||
| Aging | fa | Frequency drift over first year | 3 | ppm | |||
| fa | Frequency drift over 20 year life | 10 | ppm | ||||
| Total Stability | Temp stability = 20 ppm | 31.5 | ppm | ||||
| Total Stability | Temp stability = 7 ppm | 20 | ppm | ||||
| Powerup Time | tOSC | TA = 40C to +85C | 10 | ms | Time from powerup or tristate mode to fO. | ||
| LVPECL Output Levels | VO Mid-level | VDD 1.42 | VDD 1.25 | V | 50 to VDD 2.0 V. | ||
| VOD Swing (diff) | 1.1 | 1.9 | VPP | 50 to VDD 2.0 V. | |||
| LVDS Output Levels | VO Mid-level | 1.125 | 1.20 | 1.275 | V | Rterm = 100 (differential). | |
| VOD Swing (diff) | 0.5 | 0.7 | 0.9 | VPP | Rterm = 100 (differential). | ||
| Rise/Fall time | tR, tF | 350 | ps | ||||
| Symmetry (duty cycle) | SYM | Differential | 45 | 55 | % | ||
| Phase Jitter (RMS) | J | 10 kHz to 1 MHz (data center) | 0.19 | 0.35 | ps | Applies to output frequencies: 156.25 MHz. | |
| J | 12 kHz to 20 MHz brickwall | 0.25 | 0.40 | ps | Applies to output frequencies: 156.25 MHz. | ||
| Period Jitter (RMS) | JPER | N = 1000 cycles | 2 | ps | |||
| JPER | Peak-to-Peak | 14 | ps | N = 1000 cycles. |
2508281722_SILICON-LABS-536EC159M375DGR_C2030024.pdf
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