Si500D Differential Output Silicon Oscillator
The Si500D is a quartz-free, MEMS-free, and PLL-free all-silicon oscillator offering any output frequencies from 0.9 to 200 MHz. It provides short lead times, excellent temperature stability (20 ppm), highly reliable startup and operation, and high immunity to shock and vibration. With low jitter (<1.5 ps rms) and a wide operating temperature range (0 to 85 C including 10-year aging in hot environments), it is footprint compatible with industry-standard 3.2 x 5.0 mm XOs. Available in CMOS, SSTL, LVPECL, LVDS, and HCSL versions, it supports driver stopped, tri-state, or powerdown operation and is RoHS compliant. Options for 1.8, 2.5, or 3.3 V supply voltages and low power consumption make it a versatile solution, offering more than 10x better fit rate than competing crystal solutions.
Product Attributes
- Brand: Skyworks Solutions, Inc.
- Material: All-silicon
- Certifications: RoHS compliant
Technical Specifications
| Parameter | Condition | Min | Typ | Max | Units |
| Frequency Range | 0.9 | 200 | MHz | ||
| Frequency Stability (Temperature) | 0 to +70 C | 10 | ppm | ||
| Frequency Stability (Temperature) | 0 to +85 C | 20 | ppm | ||
| Total Stability | 0 to +70 C operation | 150 | ppm | ||
| Total Stability | 0 to +85 C operation | 250 | ppm | ||
| Operating Temperature | Commercial | 0 | 70 | C | |
| Operating Temperature | Extended commercial | 0 | 85 | C | |
| Storage Temperature | 55 | +125 | C | ||
| Supply Voltage | 1.8 V option | 1.71 | 1.98 | V | |
| Supply Voltage | 2.5 V option | 2.25 | 2.75 | V | |
| Supply Voltage | 3.3 V option | 2.97 | 3.63 | V | |
| Supply Current | LVPECL | 34.0 | 36.0 | mA | |
| Supply Current | Low Power LVPECL | 19.3 | 22.2 | mA | |
| Supply Current | LVDS | 14.9 | 16.5 | mA | |
| Supply Current | HCSL | 25.3 | 29.3 | mA | |
| Supply Current | Differential CMOS (3.3 V, 10 pF, 200 MHz) | 33 | 36 | mA | |
| Supply Current | Differential CMOS (3.3 V, 1 pF, 40 MHz) | 16 | mA | ||
| Supply Current | Differential SSTL-3.3 | 24.5 | 27.7 | mA | |
| Supply Current | Differential SSTL-2.5 | 24.3 | 26.7 | mA | |
| Supply Current | Differential SSTL-1.8 | 22.2 | 25 | mA | |
| Supply Current | Tri-State | 9.7 | 10.7 | mA | |
| Supply Current | Powerdown | 1.0 | 1.9 | mA | |
| Output Symmetry | VDIFF = 0 | 46 13 | ns/TCLK | 54 + 13 | ns/TCLK % |
| Rise and Fall Times (20/80%) | LVPECL/LVDS | 460 | ps | ||
| Rise and Fall Times (20/80%) | HCSL/Differential SSTL | 800 | ps | ||
| Rise and Fall Times (20/80%) | Differential CMOS, 15 pF, >80 MHz | 1.1 | 1.6 | ns | |
| LVPECL Output Option Mid-level | DC coupling, 50 to VDD 2.0 V | VDD 1.5 | VDD 1.34 | V | |
| LVPECL Output Option Diff swing | DC coupling, 50 to VDD 2.0 V | .720 | .880 | VPK | |
| Low Power LVPECL Output Option Mid-level | AC coupling, 100 Differential Load | N/A | V | ||
| Low Power LVPECL Output Option Diff swing | AC coupling, 100 Differential Load | .68 | .95 | VPK | |
| LVDS Output Option Mid-level | 2.5/3.3 V, RTERM = 100 diff | 1.15 | 1.26 | V | |
| LVDS Output Option Diff swing | 2.5/3.3 V, RTERM = 100 diff | 0.25 | 0.45 | VPK | |
| LVDS Output Option Mid-level | 1.8 V, RTERM = 100 diff | 0.85 | 0.96 | V | |
| LVDS Output Option Diff swing | 1.8 V, RTERM = 100 diff | 0.25 | 0.45 | VPK | |
| HCSL Output Option Mid-level | 0.35 | 0.425 | V | ||
| HCSL Output Option Diff swing | 0.65 | 0.82 | VPK | ||
| DC termination per pad | 45 | 55 | |||
| CMOS Output Voltage VOH | sourcing 9 mA | VDD 0.6 | V | ||
| CMOS Output Voltage VOL | sinking 9 mA | 0.6 | V | ||
| SSTL-1.8 Output Voltage VOH | VTT + 0.375 | V | |||
| SSTL-1.8 Output Voltage VOL | VTT 0.375 | ||||
| SSTL-2.5 Output Voltage VOH | VTT + 0.48 | V | |||
| SSTL-2.5 Output Voltage VOL | VTT 0.48 | ||||
| SSTL-3.3 Output Voltage VOH | VTT + 0.48 | V | |||
| SSTL-3.3 Output Voltage VOL | VTT 0.48 | ||||
| Powerup Time | From time VDD crosses min spec supply | 2 | ms | ||
| OE Deassertion to Clk Stop | 250 + 3 x TCLK | ns | |||
| Return from Output Driver Stopped Mode | 250 + 3 x TCLK | ns | |||
| Return From Tri-State Time | 12 + 3 x TCLK | s | |||
| Return From Powerdown Time | 2 | ms | |||
| Period Jitter (1-sigma) | Non-CMOS | 1 | 2 | ps RMS | |
| Period Jitter (1-sigma) | CMOS, CL = 7 pF | 1 | 3 | ps RMS | |
| Integrated Phase Jitter | 1.0 MHz min(20 MHz, 0.4 x FOUT), non-CMOS | 0.6 | 1 | ps RMS | |
| Integrated Phase Jitter | 1.0 MHz min(20 MHz, 0.4 x FOUT), CMOS format | 0.7 | 1.5 | ps RMS |
2508281723_SILICON-LABS-500DC00000M000AC0R_C2650825.pdf
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