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Specifications
Mfr. Part #:
570BAB001614DG
Package:
SMD7050-8P
Key Attributes
Model Number:
570BAB001614DG
Product Description
Product Overview
The Si570 XO/Si571 VCXO from Silicon Laboratories utilizes advanced DSPLL circuitry to deliver a low-jitter clock at any frequency. These devices are user-programmable to any output frequency from 10 MHz to 945 MHz, with select frequencies up to 1.4 GHz, offering <1 ppb resolution. Programming is achieved via an I2C serial interface. Unlike traditional XO/VCXOs requiring separate crystals for each frequency, the Si57x uses a single fixed-frequency crystal and DSPLL clock synthesis for universal frequency operation, ensuring exceptional frequency stability and reliability. The IC-based approach provides superior supply noise rejection, simplifying low-jitter clock generation in noisy environments common in communication systems. The Si570 is an XO (crystal oscillator), while the Si571 is a VCXO (voltage-controlled crystal oscillator) with a VC input for frequency tuning.
Product Attributes
- Brand: Silicon Laboratories
- Certifications: Pb-free/RoHS-compliant
- Package: Industry-standard 5x7 mm
Technical Specifications
| Parameter | Si570/Si571 | Min | Typ | Max | Unit | Notes |
|---|---|---|---|---|---|---|
| Electrical Specifications | ||||||
| Supply Voltage (VDD) | 3.3 V option | 2.97 | 3.3 | 3.63 | V | Selectable by part number. |
| Supply Voltage (VDD) | 2.5 V option | 2.25 | 2.5 | 2.75 | V | Selectable by part number. |
| Supply Voltage (VDD) | 1.8 V option | 1.71 | 1.8 | 1.89 | V | Selectable by part number. |
| Supply Current (IDD) | LVPECL Output Enabled | 120 | 130 | mA | ||
| Supply Current (IDD) | CML Output Enabled | 108 | 117 | mA | ||
| Supply Current (IDD) | LVDS Output Enabled | 99 | 108 | mA | ||
| Supply Current (IDD) | CMOS Output Enabled | 90 | 98 | mA | ||
| Supply Current (IDD) | TriState mode | 60 | 75 | mA | ||
| Output Enable (OE) VIH | 0.75 x VDD | V | OE pin includes a 17 k pullup resistor to VDD. | |||
| Output Enable (OE) VIL | 0.5 | V | ||||
| Operating Temperature Range (TA) | 40 | 85 | C | |||
| VC Control Voltage Input (Si571) | ||||||
| Control Voltage Tuning Slope (KV) | VC | 33 | 45 | ppm/V | Positive slope; selectable by part number. KV variation is 10% of typical. | |
| Control Voltage Tuning Slope (KV) | VC | 90 | 135 | ppm/V | Positive slope; selectable by part number. KV variation is 10% of typical. | |
| Control Voltage Tuning Slope (KV) | VC | 180 | 356 | ppm/V | Positive slope; selectable by part number. KV variation is 10% of typical. | |
| Control Voltage Linearity (BSL) | 5 | 1 | +5 | % | Determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. | |
| Control Voltage Linearity (Incremental) | 10 | 5 | +10 | % | Determined with VC ranging from 10 to 90% of VDD. | |
| Modulation Bandwidth (BW) | 9.3 | 10.0 | 10.7 | kHz | ||
| VC Input Impedance (ZVC) | 500 | k | ||||
| Nominal Control Voltage (VCNOM) | @ fO | VDD/2 | V | Nominal output frequency set by VCNOM = 1/2 x VDD. | ||
| Control Voltage Tuning Range (VC) | 0 | VDD | V | |||
| CLK Output Frequency Characteristics | ||||||
| Programmable Frequency Range (fO) | LVPECL/LVDS/CML | 10 | 1417.5 | MHz | Specified at time of order by part number. | |
| Programmable Frequency Range (fO) | CMOS | 10 | 160 | MHz | Specified at time of order by part number. | |
| Temperature Stability | TA = 40 to +85 C | 7 | +7 | ppm | Selectable parameter by part number. | |
| Temperature Stability | TA = 40 to +85 C | 20 | +20 | ppm | Selectable parameter by part number. | |
| Temperature Stability | TA = 40 to +85 C | 50 | +50 | ppm | Selectable parameter by part number. | |
| Temperature Stability | TA = 40 to +85 C | 100 | +100 | ppm | Selectable parameter by part number. | |
| Initial Accuracy | 1.5 | ppm | ||||
| Aging (fa) | Frequency drift over first year | 3 | ppm | |||
| Aging (fa) | Frequency drift over 20-year life | 10 | ppm | |||
| Total Stability | Temp stability = 7 ppm | 20 | ppm | |||
| Total Stability | Temp stability = 20 ppm | 31.5 | ppm | |||
| Total Stability | Temp stability = 50 ppm | 61.5 | ppm | |||
| Power up Time (tOSC) | From power up or tristate mode to fO | 10 | ms | |||
| CLK Output Levels and Symmetry | ||||||
| LVPECL Output Option | VOD swing (diff) | 1.1 | 1.9 | VPP | Rterm = 50 to VDD 2.0 V. | |
| LVDS Output Option | VOD swing (diff) | 0.5 | 0.7 | 0.9 | VPP | Rterm = 100 (differential). |
| CML Output Option (2.5/3.3 V) | VOD swing (diff) | 1.10 | 1.50 | 1.90 | VPP | Rterm = 100 (differential). |
| CML Output Option (1.8 V) | VOD swing (diff) | 0.35 | 0.425 | 0.50 | VPP | Rterm = 100 (differential). |
| CMOS Output Option | VOH (IOH = 32 mA) | 0.8 x VDD | VDD | V | CL = 15 pF | |
| CMOS Output Option | VOL (IOL = 32 mA) | 0.4 | V | CL = 15 pF | ||
| Rise/Fall time (20/80%) | LVPECL/LVDS/CML | 350 | ps | |||
| Rise/Fall time (20/80%) | CMOS with CL = 15 pF | 1 | ns | |||
| Symmetry (duty cycle) | LVPECL: VDD 1.3 V (diff) | 45 | 55 | % | ||
| Symmetry (duty cycle) | LVDS: 1.25 V (diff) | 45 | 55 | % | ||
| Symmetry (duty cycle) | CMOS: VDD/2 | 45 | 55 | % | ||
| CLK Output Phase Jitter (Si570) | ||||||
| Phase Jitter (RMS) | FOUT > 500 MHz (12 kHz to 20 MHz) | 0.25 | 0.40 | ps | OC-48. Refer to AN256. | |
| Phase Jitter (RMS) | FOUT > 500 MHz (50 kHz to 80 MHz) | 0.26 | 0.37 | ps | OC-192. Refer to AN256. | |
| Phase Jitter (RMS) | 125 MHz to 500 MHz (12 kHz to 20 MHz) | 0.36 | 0.50 | ps | OC-48. Refer to AN256. | |
| Phase Jitter (RMS) | 125 MHz to 500 MHz (50 kHz to 80 MHz) | 0.34 | 0.42 | ps | OC-192. Refer to AN256. | |
| Phase Jitter (RMS) | 10 MHz to 160 MHz CMOS Only (12 kHz to 20 MHz) | 0.62 | ps | OC-48. Refer to AN256. | ||
| Phase Jitter (RMS) | 10 MHz to 160 MHz CMOS Only (50 kHz to 20 MHz) | 0.61 | ps | Refer to AN256. | ||
| CLK Output Phase Jitter (Si571) | ||||||
| Phase Jitter (RMS) | FOUT > 500 MHz, Kv = 33 ppm/V (12 kHz to 20 MHz) | 0.26 | ps | Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, AN266. | ||
| Phase Jitter (RMS) | FOUT > 500 MHz, Kv = 33 ppm/V (50 kHz to 80 MHz) | 0.26 | ps | Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, AN266. | ||
| Phase Jitter (RMS) | FOUT > 500 MHz, Kv = 45 ppm/V (12 kHz to 20 MHz) | 0.27 | ps | Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, AN266. | ||
| Phase Jitter (RMS) | FOUT > 500 MHz, Kv = 45 ppm/V (50 kHz to 80 MHz) | 0.26 | ps | Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, AN266. | ||
| Phase Jitter (RMS) | FOUT > 500 MHz, Kv = 90 ppm/V (12 kHz to 20 MHz) | 0.32 | ps | Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, AN266. | ||
| Phase Jitter (RMS) | FOUT > 500 MHz, Kv = 90 ppm/V (50 kHz to 80 MHz) | 0.26 | ps | Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, AN266. | ||
| Phase Jitter (RMS) | FOUT > 500 MHz, Kv = 135 ppm/V (12 kHz to 20 MHz) | 0.40 | ps | Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, AN266. | ||
| Phase Jitter (RMS) | FOUT > 500 MHz, Kv = 135 ppm/V (50 kHz to 80 MHz) | 0.27 | ps | Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, AN266. | ||
| Phase Jitter (RMS) | FOUT > 500 MHz, Kv = 180 ppm/V (12 kHz to 20 MHz) | 0.49 | ps | Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, AN266. | ||
| Phase Jitter (RMS) | FOUT > 500 MHz, Kv = 180 ppm/V (50 kHz to 80 MHz) | 0.28 | ps | Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, AN266. | ||
| Phase Jitter (RMS) | FOUT > 500 MHz, Kv = 356 ppm/V (12 kHz to 20 MHz) | 0.87 | ps | Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, AN266. | ||
| Phase Jitter (RMS) | FOUT > 500 MHz, Kv = 356 ppm/V (50 kHz to 80 MHz) | 0.33 | ps | Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, AN266. | ||
| Applications | ||||||
| SONET/SDH | ||||||
| xDSL | ||||||
| 10 GbE LAN/WAN | ||||||
| ATE | ||||||
| High performance instrumentation | ||||||
| Low-jitter clock generation | ||||||
| Optical modules | ||||||
| Clock and data recovery | ||||||
2411220042_SILICON-LABS-570BAB001614DG_C1670562.pdf
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