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Specifications
Voltage - Supply:
1.8V~3.3V
Frequency Stability:
±10ppm
Mfr. Part #:
DSC1001CI5-033.3300
Package:
SMD3225-4P
Key Attributes
Model Number:
DSC1001CI5-033.3300
Product Description
Product Overview
The DSC1001/3/4 is a silicon MEMS-based CMOS oscillator family offering excellent jitter and stability over a wide range of supply voltages and temperatures. Its crystal-less design provides high reliability, making it suitable for rugged, industrial, and portable applications. Available in industry-standard packages, it serves as a pin-for-pin replacement for standard crystal oscillators.
Product Attributes
- Brand: Microchip Technology Inc.
- Material: Silicon MEMS
- Certifications: Pb Free, RoHS, Reach SVHC Compliant, AEC-Q100 Reliability Qualified
Technical Specifications
| Parameter | Symbol | Min | Typ | Max | Units | Conditions |
| General | ||||||
| Frequency Range | F0 | 1 | 150 | MHz | Single Frequency | |
| Frequency Tolerance | ╯f | ±10 | ppm | Includes frequency variations due to initial tolerance, temperature and power supply voltage | ||
| Frequency Tolerance | ╯f | ±20 | ppm | Includes frequency variations due to initial tolerance, temperature and power supply voltage | ||
| Frequency Tolerance | ╯f | ±25 | ppm | Includes frequency variations due to initial tolerance, temperature and power supply voltage | ||
| Frequency Tolerance | ╯f | ±50 | ppm | Includes frequency variations due to initial tolerance, temperature and power supply voltage | ||
| Aging | ╯f | ±5 | ppm | 1 year @ +25C | ||
| Standby Supply Current | IDD | 15 | µA | T = +25C | ||
| Output Startup Time | tSU | 1.0 | 1.3 | ms | T = +25C | |
| Output Disable Time | tDA | 20 | 100 | ns | ||
| Output Duty Cycle | SYM | 45 | 55 | % | ||
| Input Logic Level High | VIH | 0.75 x VDD | V | |||
| Input Logic Level Low | VIL | 0.25 x VDD | V | |||
| Supply Current, No Load (VDD = 1.8V; TA = +25C) | ||||||
| Supply Current, No Load | IDD | 6.0 | 6.3 | mA | 1 MHz, CL = 0 pF, RL = ∞ | |
| Supply Current, No Load | IDD | 6.5 | 7.1 | mA | 27 MHz, CL = 0 pF, RL = ∞ | |
| Supply Current, No Load | IDD | 7.2 | 8.5 | mA | 70 MHz, CL = 0 pF, RL = ∞ | |
| Supply Current, No Load | IDD | 8.3 | 11.9 | mA | 150 MHz, CL = 0 pF, RL = ∞ | |
| Output Logic Level High (VDD = 1.8V; TA = +25C) | ||||||
| Output Logic Level High | VOH | 0.8 x VDD | V | 6 mA, DSC1004, CL = 40 pF | ||
| Output Logic Level High | VOH | 0.8 x VDD | V | 6 mA, DSC1003, CL = 25 pF | ||
| Output Logic Level High | VOH | 0.8 x VDD | V | 4 mA, DSC1001, CL = 15 pF | ||
| Output Logic Level Low (VDD = 1.8V; TA = +25C) | ||||||
| Output Logic Level Low | VOL | 0.2 x VDD | V | 6 mA, DSC1004, CL = 40 pF | ||
| Output Logic Level Low | VOL | 0.2 x VDD | V | 6 mA, DSC1003, CL = 25 pF | ||
| Output Logic Level Low | VOL | 0.2 x VDD | V | 4 mA, DSC1001, CL = 15 pF | ||
| Output Transition Rise Time (VDD = 1.8V; TA = +25C) | ||||||
| Output Transition Rise Time | tR | 1.4 | 3.0 | ns | DSC1001, CL = 15 pF, 20% to 80% | |
| Output Transition Rise Time | tR | 1.5 | 3.0 | ns | DSC1003, CL = 25 pF, 20% to 80% | |
| Output Transition Rise Time | tR | 1.8 | 3.0 | ns | DSC1004, C2 = 40 pF, 20% to 80% | |
| Output Transition Fall Time (VDD = 1.8V; TA = +25C) | ||||||
| Output Transition Fall Time | tF | 1.0 | 3.0 | ns | DSC1001, CL = 15 pF, 20% to 80% | |
| Output Transition Fall Time | tF | 1.1 | 3.0 | ns | DSC1003, CL = 25 pF, 20% to 80% | |
| Output Transition Fall Time | tF | 1.2 | 3.0 | ns | DSC1004, C2 = 40 pF, 20% to 80% | |
| Jitter (VDD = 1.8V; TA = +25C) | ||||||
| Jitter, Max. Cycle-to-Cycle | JCC | 60 | ps | f = 100 MHz | ||
| Period Jitter | JP | 10 | 15 | psRMS | f = 100 MHz | |
| Supply Current, No Load (VDD = 2.5V; TA = +25C) | ||||||
| Supply Current, No Load | IDD | 6.0 | 6.4 | mA | 1 MHz, CL = 0 pF, RL = ∞ | |
| Supply Current, No Load | IDD | 6.7 | 7.5 | mA | 27 MHz, CL = 0 pF, RL = ∞ | |
| Supply Current, No Load | IDD | 7.7 | 9.4 | mA | 70 MHz, CL = 0 pF, RL = ∞ | |
| Supply Current, No Load | IDD | 9.6 | 13.9 | mA | 150 MHz, CL = 0 pF, RL = ∞ | |
| Output Logic Level High (VDD = 2.5V; TA = +25C) | ||||||
| Output Logic Level High | VOH | 0.9 x VDD | V | 6 mA, DSC1004, CL = 40 pF | ||
| Output Logic Level High | VOH | 0.8 x VDD | V | 6 mA, DSC1003, CL = 25 pF | ||
| Output Logic Level High | VOH | 0.8 x VDD | V | 4 mA, DSC1001, CL = 15 pF | ||
| Output Logic Level Low (VDD = 2.5V; TA = +25C) | ||||||
| Output Logic Level Low | VOL | 0.1 x VDD | V | 6 mA, DSC1004, CL = 40 pF | ||
| Output Logic Level Low | VOL | 0.2 x VDD | V | 6 mA, DSC1003, CL = 25 pF | ||
| Output Logic Level Low | VOL | 0.2 x VDD | V | 4 mA, DSC1001, CL = 15 pF | ||
| Output Transition Rise Time (VDD = 2.5V; TA = +25C) | ||||||
| Output Transition Rise Time | tR | 1.0 | 2.0 | ns | DSC1001, CL = 15 pF, 20% to 80% | |
| Output Transition Rise Time | tR | 1.1 | 2.0 | ns | DSC1003, CL = 25 pF, 20% to 80% | |
| Output Transition Rise Time | tR | 1.2 | 2.0 | ns | DSC1004, C2 = 40 pF, 20% to 80% | |
| Output Transition Fall Time (VDD = 2.5V; TA = +25C) | ||||||
| Output Transition Fall Time | tF | 0.9 | 2.0 | ns | DSC1001, CL = 15 pF, 20% to 80% | |
| Output Transition Fall Time | tF | 1.0 | 2.0 | ns | DSC1003, CL = 25 pF, 20% to 80% | |
| Output Transition Fall Time | tF | 1.1 | 2.0 | ns | DSC1004, C2 = 40 pF, 20% to 80% | |
| Jitter (VDD = 2.5V; TA = +25C) | ||||||
| Jitter, Max. Cycle-to-Cycle | JCC | 50 | ps | f = 100 MHz | ||
| Period Jitter | JP | 5 | 10 | psRMS | f = 100 MHz | |
| Supply Current, No Load (VDD = 3.3V; TA = +25C) | ||||||
| Supply Current, No Load | IDD | 6.0 | 6.5 | mA | 1 MHz, CL = 0 pF, RL = ∞ | |
| Supply Current, No Load | IDD | 6.8 | 8.0 | mA | 27 MHz, CL = 0 pF, RL = ∞ | |
| Supply Current, No Load | IDD | 8.2 | 10.5 | mA | 70 MHz, CL = 0 pF, RL = ∞ | |
| Supply Current, No Load | IDD | 10.8 | 16.6 | mA | 150 MHz, CL = 0 pF, RL = ∞ | |
| Output Logic Level High (VDD = 3.3V; TA = +25C) | ||||||
| Output Logic Level High | VOH | 0.9 x VDD | V | 8 mA, DSC1004, CL = 40 pF | ||
| Output Logic Level High | VOH | 0.9 x VDD | V | 6 mA, DSC1003, CL = 25 pF | ||
| Output Logic Level High | VOH | 0.8 x VDD | V | 4 mA, DSC1001, CL = 15 pF | ||
| Output Logic Level Low (VDD = 3.3V; TA = +25C) | ||||||
| Output Logic Level Low | VOL | 0.1 x VDD | V | 8 mA, DSC1004, CL = 40 pF | ||
| Output Logic Level Low | VOL | 0.1 x VDD | V | 6 mA, DSC1003, CL = 25 pF | ||
| Output Logic Level Low | VOL | 0.2 x VDD | V | 4 mA, DSC1001, CL = 15 pF | ||
| Output Transition Rise Time (VDD = 3.3V; TA = +25C) | ||||||
| Output Transition Rise Time | tR | 1.0 | 2.0 | ns | DSC1001, CL = 15 pF, 20% to 80% | |
| Output Transition Rise Time | tR | 1.1 | 2.0 | ns | DSC1003, CL = 25 pF, 20% to 80% | |
| Output Transition Rise Time | tR | 1.2 | 2.0 | ns | DSC1004, C2 = 40 pF, 20% to 80% | |
| Output Transition Fall Time (VDD = 3.3V; TA = +25C) | ||||||
| Output Transition Fall Time | tF | 0.9 | 2.0 | ns | DSC1001, CL = 15 pF, 20% to 80% | |
| Output Transition Fall Time | tF | 1.0 | 2.0 | ns | DSC1003, CL = 25 pF, 20% to 80% | |
| Output Transition Fall Time | tF | 1.1 | 2.0 | ns | DSC1004, C2 = 40 pF, 20% to 80% | |
| Jitter (VDD = 3.3V; TA = +25C) | ||||||
| Jitter, Max. Cycle-to-Cycle | JCC | 50 | ps | f = 100 MHz | ||
| Period Jitter | JP | 5 | 10 | psRMS | f = 100 MHz | |
| Temperature Specifications | ||||||
| Operating Temperature Range | TA | 40 | +105 | C | Ordering Option L | |
| Operating Temperature Range | TA | 40 | +85 | C | Ordering Option I | |
| Operating Temperature Range | TA | 20 | +70 | C | Ordering Option E | |
| Junction Operating Temperature | TJ | +150 | C | |||
| Storage Temperature Range | TA | 55 | +150 | C | ||
| Soldering Temperature Range | TS | +260 | C | 40 sec. max | ||
2411041600_MICROCHIP-DSC1001CI5-033-3300_C1670845.pdf
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