Product Overview
The DSC1001/3/4 is a silicon MEMS-based CMOS oscillator family offering excellent jitter and stability over a wide range of supply voltages and temperatures. Its crystal-less design provides enhanced reliability, making it suitable for rugged, industrial, and portable applications. Available in industry-standard packages, it serves as a pin-for-pin "drop-in" replacement for standard crystal oscillators.
Product Attributes
- Brand: Microchip Technology Inc.
- Material: Silicon MEMS
- Certifications: Pb Free, RoHS, Reach SVHC Compliant, AEC-Q100 Reliability Qualified
Technical Specifications
| Parameter | Symbol | Min | Typ | Max | Units | Conditions |
| Frequency Range | F0 | 1 | - | 150 | MHz | Single Frequency |
| Frequency Tolerance | Δf | - | - | ±10 | ppm | Includes variations due to initial tolerance, temperature, and power supply voltage |
| Frequency Tolerance | Δf | - | - | ±20 | ppm | Includes variations due to initial tolerance, temperature, and power supply voltage |
| Frequency Tolerance | Δf | - | - | ±25 | ppm | Includes variations due to initial tolerance, temperature, and power supply voltage |
| Frequency Tolerance | Δf | - | - | ±50 | ppm | Includes variations due to initial tolerance, temperature, and power supply voltage |
| Aging | Δf | - | - | ±5 | ppm | 1 year @ +25°C |
| Supply Current, Standby | IDD | - | - | 15 | µA | T = +25°C |
| Output Startup Time | tSU | - | 1.0 | 1.3 | ms | T = +25°C, VDD = 1.8 to 3.3V |
| Output Disable Time | tDA | - | 20 | 100 | ns | - |
| Output Duty Cycle | SYM | 45 | - | 55 | % | - |
| Input Logic Level High | VIH | 0.75 x VDD | - | - | V | - |
| Input Logic Level Low | VIL | - | - | 0.25 x VDD | V | VDD = 1.8V |
| Supply Current, No Load (1 MHz) | IDD | - | 6.0 | 6.3 | mA | VDD = 1.8V, CL = 0 pF, RL = ∞, T = +25°C |
| Supply Current, No Load (27 MHz) | IDD | - | 6.5 | 7.1 | mA | VDD = 1.8V, CL = 0 pF, RL = ∞, T = +25°C |
| Supply Current, No Load (70 MHz) | IDD | - | 7.2 | 8.5 | mA | VDD = 1.8V, CL = 0 pF, RL = ∞, T = +25°C |
| Supply Current, No Load (150 MHz) | IDD | - | 8.3 | 11.9 | mA | VDD = 1.8V, CL = 0 pF, RL = ∞, T = +25°C |
| Output Logic Level High (DSC1001) | VOH | 0.8 x VDD | - | - | V | 4 mA, CL = 15 pF, VDD = 1.8V |
| Output Logic Level High (DSC1003) | VOH | 0.8 x VDD | - | - | V | 6 mA, CL = 25 pF, VDD = 1.8V |
| Output Logic Level High (DSC1004) | VOH | 0.8 x VDD | - | - | V | 6 mA, CL = 40 pF, VDD = 1.8V |
| Output Logic Level Low (DSC1001) | VOL | - | - | 0.2 x VDD | V | 4 mA, CL = 15 pF, VDD = 1.8V |
| Output Logic Level Low (DSC1003) | VOL | - | - | 0.2 x VDD | V | 6 mA, CL = 25 pF, VDD = 1.8V |
| Output Logic Level Low (DSC1004) | VOL | - | - | 0.2 x VDD | V | 6 mA, CL = 40 pF, VDD = 1.8V |
| Output Transition Rise Time (DSC1001) | tR | - | 1.4 | 3.0 | ns | CL = 15 pF, T = +25°C, 20% to 80%, VDD = 1.8V |
| Output Transition Rise Time (DSC1003) | tR | - | 1.5 | 3.0 | ns | CL = 25 pF, T = +25°C, 20% to 80%, VDD = 1.8V |
| Output Transition Rise Time (DSC1004) | tR | - | 1.8 | 3.0 | ns | C2 = 40 pF, T = +25°C, 20% to 80%, VDD = 1.8V |
| Output Transition Fall Time (DSC1001) | tF | - | 1.0 | 3.0 | ns | CL = 15 pF, T = +25°C, 20% to 80%, VDD = 1.8V |
| Output Transition Fall Time (DSC1003) | tF | - | 1.1 | 3.0 | ns | CL = 25 pF, T = +25°C, 20% to 80%, VDD = 1.8V |
| Output Transition Fall Time (DSC1004) | tF | - | 1.2 | 3.0 | ns | C2 = 40 pF, T = +25°C, 20% to 80%, VDD = 1.8V |
| Jitter, Max. Cycle-to-Cycle | JCC | - | 60 | - | ps | f = 100 MHz, VDD = 1.8V |
| Period Jitter | JP | - | 10 | 15 | psRMS | f = 100 MHz, VDD = 1.8V |
| Supply Current, No Load (1 MHz) | IDD | - | 6.0 | 6.4 | mA | VDD = 2.5V, CL = 0 pF, RL = ∞, T = +25°C |
| Supply Current, No Load (27 MHz) | IDD | - | 6.7 | 7.5 | mA | VDD = 2.5V, CL = 0 pF, RL = ∞, T = +25°C |
| Supply Current, No Load (70 MHz) | IDD | - | 7.7 | 9.4 | mA | VDD = 2.5V, CL = 0 pF, RL = ∞, T = +25°C |
| Supply Current, No Load (150 MHz) | IDD | - | 9.6 | 13.9 | mA | VDD = 2.5V, CL = 0 pF, RL = ∞, T = +25°C |
| Output Logic Level High (DSC1001) | VOH | 0.8 x VDD | - | - | V | 4 mA, CL = 15 pF, VDD = 2.5V |
| Output Logic Level High (DSC1003) | VOH | 0.8 x VDD | - | - | V | 6 mA, CL = 25 pF, VDD = 2.5V |
| Output Logic Level High (DSC1004) | VOH | 0.9 x VDD | - | - | V | 6 mA, CL = 40 pF, VDD = 2.5V |
| Output Logic Level Low (DSC1001) | VOL | - | - | 0.2 x VDD | V | 4 mA, CL = 15 pF, VDD = 2.5V |
| Output Logic Level Low (DSC1003) | VOL | - | - | 0.2 x VDD | V | 6 mA, CL = 25 pF, VDD = 2.5V |
| Output Logic Level Low (DSC1004) | VOL | - | - | 0.1 x VDD | V | 6 mA, CL = 40 pF, VDD = 2.5V |
| Output Transition Rise Time (DSC1001) | tR | - | 1.0 | 2.0 | ns | CL = 15 pF, T = +25°C, 20% to 80%, VDD = 2.5V |
| Output Transition Rise Time (DSC1003) | tR | - | 1.1 | 2.0 | ns | CL = 25 pF, T = +25°C, 20% to 80%, VDD = 2.5V |
| Output Transition Rise Time (DSC1004) | tR | - | 1.2 | 2.0 | ns | C2 = 40 pF, T = +25°C, 20% to 80%, VDD = 2.5V |
| Output Transition Fall Time (DSC1001) | tF | - | 0.9 | 2.0 | ns | CL = 15 pF, T = +25°C, 20% to 80%, VDD = 2.5V |
| Output Transition Fall Time (DSC1003) | tF | - | 1.0 | 2.0 | ns | CL = 25 pF, T = +25°C, 20% to 80%, VDD = 2.5V |
| Output Transition Fall Time (DSC1004) | tF | - | 1.1 | 2.0 | ns | C2 = 40 pF, T = +25°C, 20% to 80%, VDD = 2.5V |
| Jitter, Max. Cycle-to-Cycle | JCC | - | 50 | - | ps | f = 100 MHz, VDD = 2.5V |
| Period Jitter | JP | - | 5 | 10 | psRMS | f = 100 MHz, VDD = 2.5V |
| Supply Current, No Load (1 MHz) | IDD | - | 6.0 | 6.5 | mA | VDD = 3.3V, CL = 0 pF, RL = ∞, T = +25°C |
| Supply Current, No Load (27 MHz) | IDD | - | 6.8 | 8.0 | mA | VDD = 3.3V, CL = 0 pF, RL = ∞, T = +25°C |
| Supply Current, No Load (70 MHz) | IDD | - | 8.2 | 10.5 | mA | VDD = 3.3V, CL = 0 pF, RL = ∞, T = +25°C |
| Supply Current, No Load (150 MHz) | IDD | - | 10.8 | 16.6 | mA | VDD = 3.3V, CL = 0 pF, RL = ∞, T = +25°C |
| Output Logic Level High (DSC1001) | VOH | 0.8 x VDD | - | - | V | 4 mA, CL = 15 pF, VDD = 3.3V |
| Output Logic Level High (DSC1003) | VOH | 0.9 x VDD | - | - | V | 6 mA, CL = 25 pF, VDD = 3.3V |
| Output Logic Level High (DSC1004) | VOH | 0.9 x VDD | - | - | V | 8 mA, CL = 40 pF, VDD = 3.3V |
| Output Logic Level Low (DSC1001) | VOL | - | - | 0.2 x VDD | V | 4 mA, CL = 15 pF, VDD = 3.3V |
| Output Logic Level Low (DSC1003) | VOL | - | - | 0.1 x VDD | V | 6 mA, CL = 25 pF, VDD = 3.3V |
| Output Logic Level Low (DSC1004) | VOL | - | - | 0.1 x VDD | V | 8 mA, CL = 40 pF, VDD = 3.3V |
| Output Transition Rise Time (DSC1001) | tR | - | 1.0 | 2.0 | ns | CL = 15 pF, T = +25°C, 20% to 80%, VDD = 3.3V |
| Output Transition Rise Time (DSC1003) | tR | - | 1.1 | 2.0 | ns | CL = 25 pF, T = +25°C, 20% to 80%, VDD = 3.3V |
| Output Transition Rise Time (DSC1004) | tR | - | 1.2 | 2.0 | ns | C2 = 40 pF, T = +25°C, 20% to 80%, VDD = 3.3V |
| Output Transition Fall Time (DSC1001) | tF | - | 0.9 | 2.0 | ns | CL = 15 pF, T = +25°C, 20% to 80%, VDD = 3.3V |
| Output Transition Fall Time (DSC1003) | tF | - | 1.0 | 2.0 | ns | CL = 25 pF, T = +25°C, 20% to 80%, VDD = 3.3V |
| Output Transition Fall Time (DSC1004) | tF | - | 1.1 | 2.0 | ns | C2 = 40 pF, T = +25°C, 20% to 80%, VDD = 3.3V |
| Jitter, Max. Cycle-to-Cycle | JCC | - | 50 | - | ps | f = 100 MHz, VDD = 3.3V |
| Period Jitter | JP | - | 5 | 10 | psRMS | f = 100 MHz, VDD = 3.3V |
| Operating Temperature Range | TA | -40 | - | +105 | °C | - |
| Operating Temperature Range (Option L) | TA | -40 | - | +85 | °C | Ordering Option L |
| Operating Temperature Range (Option I) | TA | -40 | - | +85 | °C | Ordering Option I |
| Operating Temperature Range (Option E) | TA | -20 | - | +70 | °C | Ordering Option E |
| Junction Operating Temperature | TJ | - | - | +150 | °C | - |
| Storage Temperature Range | TA | -55 | - | +150 | °C | - |
| Soldering Temperature Range | TS | - | - | +260 | °C | 40 sec. max |
2411041601_MICROCHIP-DSC1001CL2-100-0000T_C611699.pdf
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