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Specifications
Voltage Rating:
10V
Capacitance:
22uF
Temperature Coefficient:
X5R
Tolerance:
±10%
Mfr. Part #:
TCC0805X5R226K100FT
Package:
0805
Key Attributes
Model Number:
TCC0805X5R226K100FT
Product Description
Product Overview
The Multi-Layer Ceramic Capacitors (MLCC) offered are designed for a wide range of electronic applications. They are categorized into Class I (COG/NPO) and Class II (X7R, X7S, X7T, X6R, X6S, X6T, X5R) dielectrics, providing stable electrical properties or higher capacitance values respectively. Class I capacitors are ideal for low-loss, high-stability circuits like filters, oscillators, and timing circuits. Class II capacitors are suitable for DC-blocking, decoupling, bypassing, and frequency discriminating circuits where a broad capacitance range and less stringent stability requirements are acceptable.
Product Attributes
- Brand: CCTC ()
- Manufacturer: Chaozhou Three-Circle (Group) Co., Ltd.
- Certifications: RoHS, REACH, Halogen-free (mentioned in revision history)
Technical Specifications
| Document No. | Document Name | Version | Change Date | Pages | Content of Change | Registrant |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | B/0 | 2012/01/11 | 38 | New Set | Qianjun Fang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | B/1 | 2012/08/11 | 36 | Added the carrier tape dimension of 2225 and 1808 sizes | Binbin Wang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | C/0 | 2013/01/10 | 39 | Version Change | Binbin Wang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | D/0 | 2014/01/06 | 39 | Updated the SGS Report | Binbin Wang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | E/0 | 2014/05/06 | 44 | Version Change | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | F/0 | 2015/02/10 | 44 | Version Change | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | G/0 | 2016/05/15 | 44 | Version Change | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | H/0 | 2017/07/01 | 44 | Version Change | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | I/0 | 2020/02/12 | 44 | Version Change | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | J/0 | 2021/01/07 | 39 | Add 0201 size and X6S/X7T dielectrics; deleted dimensions above 1210 size | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | J/1 | 2021/03/25 | 39 | Added the specification model of 0201 size and COG dimension | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | K/0 | 2022/03/18 | 39 | Version Change | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | K/1 | 2022/06/28 | 41 | Version Change | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | K/2 | 2022/08/29 | 59 | Updated the range of capacitance | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | K/3 | 2022/11/28 | 59 | Added requirements of the RoHS, REACH and HF | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | L/0 | 2023/1/16 | 59 | Version Change | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | L/1 | 2023-02-01 | 57 | Update capacity | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | L/2 | 2023-02-24 | 57 | Update 0105 capacity | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | L/3 | 2023-05-13 | 54 | Update capacity, increase the tolerance range of crest welding and reflow welding, and add the introduction of standard remarks | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | M/0 | 2023-09-15 | 61 | Update capacity, Shenzhen base address and medium box package size | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | M/1 | 2023-12-08 | 53 | Update capacity, Belt size | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | M/2 | 2024-04-11 | 54 | Update capacity | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | M/3 | 2024-08-05 | 54 | Update capacity | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | M/4 | 2024-09-25 | 55 | Update capacity, Dimensions of Reel, Matters needing attention | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | N/0 | 2025-01-16 | 55 | Update capacity, Belt size | Jiarui Chen |
| Document No. | Types of Capacitor and Dielectric Material | Description |
| DRAAW108N/0 | COG (NPO) - Class I | Most stable electrical properties, little change with temperature, voltage, and time. Suited for low-loss, high-stability applications (filters, oscillators, timing circuits). |
| DRAAW108N/0 | X7R, X7S, X7T, X6R, X6S, X6T, X5R - Class II | High dielectric constant, higher capacitance than Class I. Semi-stable temperature characteristic. Used over a wide temperature range for DC-blocking, decoupling, bypassing, frequency discriminating circuits. |
| Document No. | Product Parts Numbering System Example | Component | Description |
| DRAAW108N/0 | TCC 0805 X5R 105 M 500 F T | Code of Ceramic Capacitor | TCC |
| DRAAW108N/0 | TCC 0805 X5R 105 M 500 F T | Chip Size | 0805=2.001.25mm |
| DRAAW108N/0 | TCC 0805 X5R 105 M 500 F T | Type=LW | X5R |
| DRAAW108N/0 | TCC 0805 X5R 105 M 500 F T | Capacitance | 105=10105 pF =1,000,000pF (105 indicates 10 followed by 5 zeros) |
| DRAAW108N/0 | TCC 0805 X5R 105 M 500 F T | Temperature Characteristic | COG(NPO), X7R,X7S,X7T,X6R,X6S,X6T,X5R |
| DRAAW108N/0 | TCC 0805 X5R 105 M 500 F T | Capacitance Tolerance | A=0.05pF, B=0.1pF, C=0.25pF, D=0.5pF, F=1.0%, G=2.0%, J=5.0%, K=10%, M=20%, Z=-20/+80% |
| DRAAW108N/0 | TCC 0805 X5R 105 M 500 F T | Thickness | Y:0.20mm, Z:0.30mm, A:0.50mm, B:0.60mm, C:0.80mm, D:0.85mm, E:1.00mm, F:1.25mm, H:1.60mm, G:2.00mm, M:2.50mm |
| DRAAW108N/0 | TCC 0805 X5R 105 M 500 F T | Rated Voltage | 2R5=2.5VDC, 4R0=4.0VDC, 6R3=6.3VDC, 100=10VDC, 160=16VDC, 250=25VDC, 350=35VDC, 500=50VDC, 101=100VDC, 201=200VDC, 251=250VDC, 501=500VDC, 631=630VDC, 102=1000VDC, 202=2000VDC |
| DRAAW108N/0 | TCC 0805 X5R 105 M 500 F T | Packing | B: bulk packaging in a bag, T: tape carrier Packaging of small reel, W: tape carrier Packaging of big reel |
| Document No. | Dielectrics Characteristic Group | Dielectrics | Operating Temperature Range | Temperature Characteristic |
| DRAAW108N/0 | COGNPO | COGNPO | -55~+125 | 030ppm/ |
| DRAAW108N/0 | X7R | X7R | -55~+125 | 15% |
| DRAAW108N/0 | X7S | X7S | -55~+125 | 22% |
| DRAAW108N/0 | X7T | X7T | -55~+125 | +22/-33% |
| DRAAW108N/0 | X6R | X6R | -55~+105 | 15% |
| DRAAW108N/0 | X6S | X6S | -55~+105 | 22% |
| DRAAW108N/0 | X6T | X6T | -55~+105 | +22/-33% |
| DRAAW108N/0 | X5R | X5R | -55~+85 | 15% |
| Document No. | Size | Dielectric | Capacitance (Cp/VDC) |
| DRAAW108N/0 | 0105(0402) | COG | 0R1, 0R2, 0R3, 0R4, 0R5, 0R6, 0R7, 0R8, 0R9, 1R0, 1R1, 1R2, 1R3, 1R5, 1R6, 1R8, 2R0, 2R2, 2R4, 2R7, 3R0, 3R3, 3R6 (for various VDC: 50, 35, 25, 16, 10, 6.3) |
| DRAAW108N/0 | 0105(0402) | X7R | 0R1, 0R2, 0R3, 0R4, 0R5, 0R6, 0R7, 0R8, 0R9, 1R0, 1R1, 1R2, 1R3, 1R5, 1R6, 1R8, 2R0, 2R2, 2R4, 2R7, 3R0, 3R3, 3R6 (for various VDC: 50, 35, 25, 16, 10, 6.3) |
| DRAAW108N/0 | 0105(0402) | X6T | 0R1, 0R2, 0R3, 0R4, 0R5, 0R6, 0R7, 0R8, 0R9, 1R0, 1R1, 1R2, 1R3, 1R5, 1R6, 1R8, 2R0, 2R2, 2R4, 2R7, 3R0, 3R3, 3R6 (for various VDC: 50, 35, 25, 16, 10, 6.3) |
| DRAAW108N/0 | 0105(0402) | X5R | 0R1, 0R2, 0R3, 0R4, 0R5, 0R6, 0R7, 0R8, 0R9, 1R0, 1R1, 1R2, 1R3, 1R5, 1R6, 1R8, 2R0, 2R2, 2R4, 2R7, 3R0, 3R3, 3R6 (for various VDC: 50, 35, 25, 16, 10, 6.3) |
2510151120_CCTC-TCC0805X5R226K100FT_C380336.pdf
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