Multi-Layer Ceramic Capacitors - Specification for Approval
This document outlines the specifications for Multi-Layer Ceramic Capacitors (MLCCs). It details product classifications, structure, part numbering system, capacitance ranges, dimensions, technical requirements, testing conditions, packaging, and usage precautions.
Product Attributes
- Manufacturer: (Chaozhou Three-Circle (Group) Co., Ltd.)
- Product Name: (Multi-Layer Ceramic Capacitors)
- Product Specification: (General Series)
- Approval Sheet No.: DRAAW108N/0
- Issued Date: Refer to revision history
- Manufacturer Addresses:
- Headquarters: () (Fengtang Three-Circle Industrial City, Chaozhou, Guangdong, China (Chaozhou Headquarters))
- Nanchang Base: (Nanchang Three-Circle Group Third Factory Area, Qingxi Street, Gaoping District, Nanchong City, Sichuan Province (Nanchang Base))
- Shenzhen Base: (Three-Circle Technology Building, Jiatang Community, Fenghuang Street, Guangming District, Shenzhen (Shenzhen Base))
- Contact Information:
- Headquarters Phone: 86-768-6855932
- Headquarters Fax: 86-768-6855921
- Website: HTTP://WWW.CCTC.CC
- Certifications: RoHS, REACH, Halogen-Free (as per revision K/3)
Technical Specifications
| Document No. | Document Name | Version | Change Date | Pages | Content of Change | Registrant |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | B/0 | 2012/01/11 | 38 | New Set | Qianjun Fang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | B/1 | 2012/08/11 | 36 | Added the carrier tape dimension of 2225 and 1808 sizes | Binbin Wang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | C/0 | 2013/01/10 | 39 | Version Change | Binbin Wang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | D/0 | 2014/01/06 | 39 | Updated the SGS Report | Binbin Wang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | E/0 | 2014/05/06 | 44 | Version Change | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | F/0 | 2015/02/10 | 44 | Version Change | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | G/0 | 2016/05/15 | 44 | Version Change | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | H/0 | 2017/07/01 | 44 | Version Change | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | I/0 | 2020/02/12 | 44 | Version Change | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | J/0 | 2021/01/07 | 39 | Add 0201 size and X6S/X7T dielectrics; deleted dimensions above 1210 size | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | J/1 | 2021/03/25 | 39 | Added the specification model of 0201 size and COG dimension | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | K/0 | 2022/03/18 | 39 | Version Change | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | K/1 | 2022/06/28 | 41 | Version Change | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | K/2 | 2022/08/29 | 59 | Updated the range of capacitance | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | K/3 | 2022/11/28 | 59 | Added requirements of the RoHS, REACH and HF | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | L/0 | 2023/1/16 | 59 | Version Change | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | L/1 | 2023-02-01 | 57 | Update capacity | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | L/2 | 2023-02-24 | 57 | Update 0105 capacity | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | L/3 | 2023-05-13 | 54 | Update capacity, increase the tolerance range of crest welding and reflow welding, and add the introduction of standard remarks | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | M/0 | 2023-09-15 | 61 | Update capacity, Shenzhen base address and medium box package size | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | M/1 | 2023-12-08 | 53 | Update capacity, Belt size | Guoxin Zhang |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | M/2 | 2024-04-11 | 54 | Update capacity | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | M/3 | 2024-08-05 | 54 | Update capacity | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | M/4 | 2024-09-25 | 55 | Update capacity, Dimensions of Reel, Matters needing attention | Jiarui Chen |
| DRAAW108N/0 | Specification for Multilayer Ceramic Chip Set | N/0 | 2025-01-16 | 55 | Update capacity, Belt size | Jiarui Chen |
Product Categories and Dielectric Materials
Class I Capacitors (COG/NPO)
Characteristics: Highly stable electrical properties, minimal change with temperature, voltage, and time. Low loss.
Applications: Circuits requiring high stability and low loss, such as filters, oscillators, and timing circuits.
Class II Capacitors (X7R, X7S, X7T, X6R, X6S, X6T, X5R)
Characteristics: High dielectric constant, higher capacitance than Class I. Semi-stable temperature characteristics. Suitable for a wide capacitance range.
Applications: Circuits where capacitance range is broad and stability requirements are not as critical, such as DC-blocking, decoupling, bypassing, and frequency discriminating circuits.
Product Structure
The product structure consists of:
- Ceramic dielectric
- Inner electrode
- Outer electrode
- Nickel layer
- Tin layer
General Product Parts Numbering System
Example: TCC 0805 X5R 105 M 500 F T
Note: It is recommended that the operating temperature drop limit is less than 20 and the operating voltage drop limit is more than 30%.
Code Definitions:
- Ceramic Capacitor Code: TCC
- Chip Size (LW): 0105=0.400.20mm, 0201=0.600.30mm, 0402=1.000.50mm, 0603=1.600.80mm, 0805=2.001.25mm, 1206=3.201.60mm, 1210=3.202.50mm, 1812=4.503.20mm, 2220=5.705.00mm
- Capacitance: e.g., 105 = 10 10^5 pF = 1,000,000 pF (Two significant digits followed by the number of zeros)
- Temperature Characteristic: COG(NPO), X7R, X7S, X7T, X6R, X6S, X6T, X5R
- Capacitance Tolerance: A=0.05pF, B=0.1pF, C=0.25pF, D=0.5pF, F=1.0%, G=2.0%, J=5.0%, K=10%, M=20%, Z=-20/+80%
- Thickness: Y:0.20mm, Z:0.30mm, A:0.50mm, B:0.60mm, C:0.80mm, D:0.85mm, E:1.00mm, F:1.25mm, H:1.60mm, G:2.00mm, M:2.50mm
- Rated Voltage: 2R5=2.5VDC, 4R0=4.0VDC, 6R3=6.3VDC, 100=10VDC, 160=16VDC, 250=25VDC, 350=35VDC, 500=50VDC, 101=100VDC, 201=200VDC, 251=250VDC, 501=500VDC, 631=630VDC, 102=1000VDC, 202=2000VDC
- Packing: B: Bulk packaging in a bag, T: Tape carrier packaging of small reel, W: Tape carrier packaging of big reel
Dielectric Characteristics Group
| Dielectrics | Operating Temperature Range | Temperature Coefficient or Temperature Characteristic |
| COG(NPO) | -55~+125 | 030ppm/ |
| X7R | -55~+125 | 15% |
| X7S | -55~+125 | 22% |
| X7T | -55~+125 | +22/-33% |
| X6R | -55~+105 | 15% |
| X6S | -55~+105 | 22% |
| X6T | -55~+105 | +22/-33% |
| X5R | -55~+85 | 15% |
Product Capacitance Range
Note: Above capacitance for reference only, actual capacitance range depends on the use requirement.
Size 0105 (0402)
| Cp/VDC | COG Series | X7R Series | X6T Series | X5R Series |
| 50 | Y | Y | Y | Y |
| 35 | Y | Y | Y | Y |
| 25 | Y | Y | Y | Y |
| 16 | Y | Y | Y | Y |
| 10 | Y | Y | Y | Y |
| 6.3 | Y | Y | Y | Y |
| 0R1 | Y | Y | Y | Y |
| 0R2 | Y | Y | Y | Y |
| 0R3 | Y | Y | Y | Y |
| 0R4 | Y | Y | Y | Y |
| 0R5 | Y | Y | Y | Y |
| 0R6 | Y | Y | Y | Y |
| 0R7 | Y | Y | Y | Y |
| 0R8 | Y | Y | Y | Y |
| 0R9 | Y | Y | Y | Y |
| 1R0 | Y | Y | Y | Y |
| 1R1 | Y | Y | Y | Y |
| 1R2 | Y | Y | Y | Y |
| 1R3 | Y | Y | Y | Y |
| 1R5 | Y | Y | Y | Y |
| 1R6 | Y | Y | Y | Y |
| 1R8 | Y | Y | Y | Y |
| 2R0 | Y | Y | Y | Y |
| 2R2 | Y | Y | Y | Y |
| 2R4 | Y | Y | Y | Y |
| 2R7 | Y | Y | Y | Y |
| 3R0 | Y | Y | Y | Y |
| 3R3 | Y | Y | Y | Y |
| 3R6 | Y | Y | Y | Y |
2510151120_CCTC-TCC0402X5R334K250AT_C5448882.pdf
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